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STA016T
MPEG 2.5 LAYER III AUDIO DECODER SUPPORTING CD-ROM CAPABILITY & ADPCM
PRODUCT PREVIEW
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SINGLE CHIP MPEG LAYER 3 DECODER SUPPORTING: - All features specified for Layer III in ISO/IEC 11172-3 (MPEG 1 Audio) - All features specified for Layer III in ISO/IEC 13818-3.2 (MPEG 2 Audio) - Lower sampling frequencies syntax extension, (not specified by ISO) called MPEG 2.5 DECODES LAYER III STEREO CHANNELS, DUAL CHANNEL, SINGLE CHANNEL (MONO) SUPPORTING ALL THE MPEG 1 & 2 SAMPLING FREQUENCIES AND THE EXTENSION TO MPEG 2.5:48, 44.1,32, 24,22.05, 16, 12,11. 025, 8 KHz ACCEPTS MPEG 2.5 LAYER III ELEMENTARY COMPRESSED BITSTREAM WITH DATA RATE FROM 8 Kbit/s UP TO 320 Kbit/s BYPASS MODE FOR EXTERNAL AUXILIARY AUDIO SOURCE ADPCM ENCODING/DECODING CAPABILITY: - sample frequency from 8 kHz to 32 kHz - sample size from 8 bits to 32 bits - encoding algorithm: DVI, ITU-G726 pack (G723-24, G721,G723-40) EMBEDDED ISO9660 LAYER FOR FILESYSTEM DECODING (JOLIET) EMBEDDED CD-ROM DECODER BLOCKS INCLUDING ECC/EDC CAPABILITY FLEXIBLE I2S INPUT INTERFACE FOR EASY CONNECTION WITH MOST CD-SERVO DEVICES EMBEDDED BROWSING COMMAND INTERPRETER FOR EASY FILE-SYSTEM BROWSING CUE-SHEET CAPABILITY UP TO 100 ENTRIES BROWSER COMMAND INTERPRETER (BCI) - Parent Dir - Enter Dir - Previous Entry - Next Entry - Get Record Infos
TQFP64
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EASY PROGRAMMABLE GPSO INTERFACE (MONO/STEREO) FOR ENCODED DATA UP TO 5Mbit/s DIGITAL VOLUME BASS & TREBLE CONTROL SERIAL BITSTREAM INPUT INTERFACE EASY PROGRAMMABLE ADC INPUT INTERFACE SERIAL PCM OUTPUT INTERFACE (I2S AND OTHER FORMATS) PLL FOR INTERNAL CLOCK AND FOR OUTPUT PCM CLOCK GENERATION CRC CHECK AND SYNCHRONISATION ERROR DETECTION WITH SOFTWARE INDICATORS I2C CONTROL BUS LOW POWER 2.4V CMOS TECHNOLOGY WITH 3.3V TOLERANT AND CAPABLE I/O FAST FORWARD AND PAUSE CAPABILITIES
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ORDERING NUMBER: STA016T
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APPLICATIONS
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AUDIO CD PLAYERS MULTIMEDIA PLAYERS CD-ROM PLAYERS CAR RADIO PLAYERS
November 2002
This is preliminary information on a new product foreseen to be developed. Details are subject to change without notice.
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STA016T
DESCRIPTION
The STA016 is a single chip MPEG 1, 2 and 2.5 Layer III audio decoder with embedded CDROM decoding capability. It can be easily connected to most existing CDDSP devices via a software configurable serial link. A tipical application block diagram is show in Figure 1. Besides MPEG decoding the device can also perform ADPCM encoding/decoding from different audio sources and the encoded stream, for instance, can be stored on an external flash memory. A useful bypass mode allow using this device also as an audio processor for volume and tone controls.
Figure 1. Typical CD-Player application
CD Mechanic
TUNER MODULE OR AUX. AUDIO SOURCE
CDDSP I/F CDDSP
I2S OUT
D/A
L R
STA016
I2C SDI MCU GPSO FLASH MEMORY for MP3 files or ADPCM encoded messages (optional) CD MODULE
ABSOLUTE MAXIMUM RATINGS
Symbol VDD VCC PLL-V CC VIH/VIL Tstg Top Tj Parameter Digital Power Supply at 2.5V (nominal) Digital Power Supply at 3.3V (nominal) Analog Supply Voltage at 2.5V (nominal) Voltage on input pins (3.3V pads) Storage Temperature Operative ambient temp Operating Junction Temperature Value -0.5 to 3.3 -0.5 to 4 -0.5 to 3.3 -0.5 to VCC +0.5 -40 to +150 -40 to +85(*) -40 to 125 Unit V V V V C C C
(*) guaranteed by design
THERMAL DATA
Symbol Rth j-amb Parameter Thermal resistance Junction to Ambient Value 85 Unit C/W
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1 OVERVIEW
The device can decode/process data coming from three possible sources, as showed in Figure 2: s CDDSP serial link: using this input interface, besides MP3 encoded data CD, it's possible to playback also standard Audio CD using the available volume and tone equalizer features of the device and allowing the use of only one D/A converter with no external analog switch.
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SDI input interface: through this input interface it's possible to decode any MP3 bitstream coming, for instance, from an external flash memory. This same interface is also used to decode ADPCM streams. I2S input interface: this interface can be used both to encode an external audio source (with variable compression based on 4 different ADPCM algorithm) or to process an external audio source (tuner, for instance) through the DSP based volume and tone controls:this BYPASS mode can avoid the use of additional D/A converters or postprocessing units.
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1.1 MP3 decoder engine
The MP3 decoder engine is able to decode any Layer III compliant bitstream: MPEG1, MPEG2 and MPEG2.5 streams are supported. Decoded audio data goes through a software volume control and a two-band equalizer blocks before feeding the output I2S interface. This results in no need for an external audio processor.
Table 1. MPEG Sampling Rates (KHz)
MPEG 1 48 44.1 32 MPEG 2 24 22.05 16 MPEG 2.5 12 11.025 8
1.2 ADPCM encoder/decoder engine
This device also embeds a multistandard ADPCM encoder/decoder supporting different sample rates (from 8 KHz up to 32 KHz) and different sample sizes (from 8 bit to 32 bits). During encoding process two different interfaces can be used to feed data: the serial input interface (same interface used also to feed MP3 bitstream) or the ADC input interface, which provides a seamless connection with an external A/D converter. The currently used interface is selected via I2C bus. Also to retrieve encoded data a specific interface is available: the fast GPSO output interface. GPSO interface is able to output data with a bitrate up to 5 Mbit/s and its control pins (GPSO_SCKR, GPSO_DATA and GPSO_REQ) can be configured in order to easily fit the target application.
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Figure 2. Block Diagram
CDROM DECODER (C3) CD_BCK CD_SDI CD_LRCK SECTOR BUFFER BS_BCK BS_SDI BS_LRCK DREQ BCKI SDI LRCKI STB RQST SCL SDA GPSO_CK I2C I/F I2C REG BANK PLL OSC GPSO I/F GPSO_SDO GPSO_REQ I2S IN I/F MMDSP CORE - ISO9660 + JOLIET - BCI - MP3 + ADPCM SDI I/F INPUT SELECTOR CDDSP I/F SYNC DETECT. DESCRAM. ECC/EDC
BCKO PCM OUTPUT BUFFER I2S OUT I/F SDO LRCKO
OSCK
XTI
XTO
D00AU1221
The basic functions of the device can be fully operated via the I2C bus. Besides that the GPSO interface can be used to move huge amount of data this fast and flexible interface can achieve transfer rates up to 5 Mbit/s. The embedded DSP firmware implements all the layers required to decode a standard data CD, as shown in the Figure 3:
Figure 3. Layers performed by embedded DSP firmware
FRAMES to SECTOR TRANSLATOR
SYNC DETECTOR DESCRAMBLER EDC/ECC (C3) ISO9660 File System Decoding (with Joliet support) Browsing Command Interface
The whole CDROM and file-system decoding task is performed by embedded firmware. The application MCU, basically, must manage CDDSP device according to STA016 requests. Three basic command flows exist: s MCU -> STA016: commands used to handle decoder operation and to ask for specific information like filename, filelength, sector raw data, etc. This flow will use I2C (GPSO for special operations) interface.
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STA016 -> MCU: this channel is used to retrieve inquired information and to inform MCU that a CDDSP
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specific operation must be performed (like pick-up repositioning). This flow is based on I2C link plus an additional interrupt signal in order to avoid time consuming polling techniques.
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MCU -> CDDSP: the CDDSP management is fully up to the application MCU. This architecture allows maximum flexibility and easy migration from existing CDPlayers to MP3 CDPlayers.
PIN CONNECTION
GPSO_REQ GPSO_SDO IODATA15 IODATA14 IODATA13 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 IODATA0 IODATA1 IODATA2 IODATA3 IODATA4 XTO OSCK BCKO SDO XTI VSS_3 VCC_1 CLKOUT LRCKO VDD_3 VSS_4 GPSO_CK
VDD_6
VCC_3
VDD_5
VSS_9
VSS_8
64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 CD_LRCK CD_BCK CD_SDI DREQ VDD_1 VSS_1 BS_LRCK BS_BCK BS_SDI VDD_2 VSS_2 LRCK1 BCKI SDI RESET TESTEN 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 IODATA12 IODATA11 IODATA10 IODATA9 IODATA8 VSS_6 VCC_2 PLL_GND FILT0 PLL_VCC FILT1 VSS_5 VDD_4 IODATA7 IODATA6 IODATA5
VSS_7
RQST
SDA
STB
SCL
D00AU1227
PIN DESCRIPTION
PIN Pin Name Type Description CDDSP interface 1 3 2 CD_LRCK CD_SDI CD_BCK I I I DSP Interface left/right Clock DSP interface serial data DSP interface bit clock SDI interface 9 7 8 4 BS_SDI BS_LRCK BS_BCK DREQ I I I O Bitstream interface serial data Bitstream interface left/right Clock Bitstream interface clock Bitstream data request PCM IN interface 13 BCKI I ADC bit clock From ADC From MCU From MCU From MCU To MCU From DSP From DSP From DSP Sourde/Dest
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PIN DESCRIPTION (continued)
PIN 14 12 Pin Name SDI LRCKI Type I I ADC serial data ADC left/right Clock PCM OUT interface 20 22 21 19 LRCKO SDO BCKO OSCK O O O O DAC Interface left/right Clock DAC serial data DAC bit clock DAC oversampling clock GPSO interface 55 54 56 GPSO_CK GPSO_SDO GPSO_REQ I O O GPSO bit clock GPSO serial data GPSO request signal GPIO interface 26 27 28 31 32 33 34 35 44 45 46 47 48 49 50 51 IODATA0 IODATA1 IODATA2 IODATA3 IODATA4 IODATA5 IODATA6 IODATA7 IODATA8 IODATA9 IODATA10 IODATA11 IODATA12 IODATA13 IODATA14 IODATA15 I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O GPIODATA0 GPIODATA1 GPIODATA2 GPIODATA3 GPIODATA4 GPIODATA5 GPIODATA6 GPIODATA7 GPIODATA8 GPIODATA9 GPIODATA10 GPIODATA11 GPIODATA12 GPIODATA13 GPIODATA14 GPIODATA15 From MCU To MCU To MCU To DAC To DAC To DAC To DAC/ADC Description Sourde/Dest From ADC From ADC
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PIN DESCRIPTION (continued)
PIN Pin Name Type Description HANDSHAKE SIGNALS 60 59 STB RQST I O Strobe signal I2C data signal I2C LINK 63 64 SCL SDA I I/O I2C clock signal I2C data signal MISCELLANEOUS 17 18 25 15 16 40 38 XTI XTO CLKOUT -RESET -TESTEN FILT0 FILT1 I O O I I I Oscillator input Oscillator output Buffered output clock Reset Reserved for test purpose PLL external filter PLL external filter POWER SUPPLY 39 41 5 10 29 36 53 62 23 42 58 6 11 24 30 37 43 52 57 61 PLL_VCC PLL_GND VDD_1 VDD_2 VDD_3 VDD_4 VDD_5 VDD_6 VCC_1 VCC_2 VCC_3 VSS_1 VSS_2 VSS_3 VSS_4 VSS_5 VSS_6 VSS_7 VSS_8 VSS_9 Digital supply (2.5V Power Supply) Ground Digital supply (2.5V Power Supply) Digital supply (2.5V Power Supply) Digital supply (2.5V Power Supply) Digital supply (2.5V Power Supply) Digital supply (2.5V Power Supply) Digital supply (2.5V Power Supply) Digital supply (3.3V Power Supply) Digital supply (3.3V Power Supply) Digital supply (3.3V Power Supply) Ground Ground Ground Ground Ground Ground Ground Ground Ground From MCU To MCU From MCU To MCU Sourde/Dest
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ELECTRICAL CHARACTERISTCS
(Tamb = 25C; Rg = 50 unless otherwise specified)
DC OPERATING CONDITIONS
Symbol VDD VCC PLL_V CC Power Supply Voltage Power Supply Voltage Power Supply Voltage Parameter Value 2.5 0.25 3.3 0.3 2.5 0.25 Unit V V V
GENERAL INTERFACE ELECTRICAL CHARACTERISTICS
Symbol IIL IIH Vesd Parameter Low Level Input CurrentWithout pull-up device High Level Input CurrentWithout pull-up device Electrostatic Protection Test Condition Vi = 0V Vi = VDD Leakage < 1A Min. -10 -10 2000 Typ. Max. 10 10 Unit A A V Note 1 1 2
Note 1: The leakage currents are generally very small, < 1nA. The value given here is a maximum that can occur after an electrostatic stress on the pin. Note 2: Human Body Model.
DC ELECTRICAL CHARACTERISTICS
Symbol VIL VIH Vol Voh Parameter Low Level Input Voltage High Level Input Voltage Low Level Output Voltage High Level Output Voltage Iol = Xma
0.85*V CC
Test Condition
Min.
Typ.
Max.
0.2*VCC
Unit V V
Note
0.8*VCC
0.4V
V V
1, 2 1, 2
Note1: Takes into account 200mV voltage drop in both supply lines. Note 2: X is the source/sink current under worst case conditions and is reflected in the name of the I/O cell according to the drive capability.
Symbol Ipu Rpu
Parameter Pull-up current Equivalent Pull-up Resistance
Test Condition Vi = 0V; pin numbers 7, 24 and 26
Min. -25
Typ. -66 50
Max. -125
Unit A k
Note 1
Note 1: Min. condition: VDD = 2.7V, 125C Min process Max. condition: VDD = 3.6V, -20C Max.
POWER DISSIPATION
Symbol PD Parameter
Power Dissipation@ VDD = 2.4V
Test Condition Sampling_freq 24 kHz Sampling_freq 32 kHz Sampling_freq 48 kHz
Min.
Typ. t.b.d. t.b.d. t.b.d.
Max.
Unit mW mW mW
Note
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2 HOST REGISTERS
The following table gives a description of STA016 register list. The STA016 device includes 256 I2C registers. In this document, only the user-oriented registers are described. The undocumented registers are reserved or unused. These registers must never be accessed (in Read or in Write mode). The Read-Only registers must never be written We can split the data flux in different time periods (see following diagram) meanwhile host registers can be read or written : s DWT : During Whole Time (at any time during process).
s s s s s s
DEC : During External Config (period between RUN=2 and RUN=1). DBO : During Boot (period between RUN=0 and RUN=2). ABO : After BOot (period after RUN=1). AEC : After External Config (period after RUN=2). EDF : Every Decoded Frame (each time a frame has been decoded). EDB : Every Decoded Block (each time a block has been decoded).
SOFT_RESET = 1 CK_CMD = 0 block1 frame1 block2 frame1 block1 frame2
HR
RUN==0
RUN==2
RUN==1
time
DWT DBO DEC ABO AEC
D01AU1260
EDB
EDB EDF
EDB
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REGISTER MAP BY FUNCTION
Register function VERSION Hex 0x00 0x01 0xD3 PLL_AUDIO_CONFIGURATION 0xDC 0xDD 0xDE 0xDF 0xE0 0xE1 0xE2 0xE3 0xE4 0xE5 PLL_SYSTEM_CONFIGURATION 0xE6 0xE7 0xE8 0xE9 0xEA 0xEB 0xEC 0xED 0xEE 0xEF I2Sout_CONFIGURATION 0x66 0x67 0x68 0x69 GPSO_CONFIGURATION 0x66 0x6A I2Sin_CONFIGURATION 0x5A 0x5B 0x5C 0x5D Dec 0 1 211 220 221 222 223 224 225 226 227 228 229 230 231 232 233 234 235 236 237 238 239 102 103 104 105 102 106 90 91 92 93 VERSION IDENT SOFT_VERSION PLL_AUDIO_PEL_192 PLL_AUDIO_PEH_192 PLL_AUDIO_NDIV_192 PLL_AUDIO_XDIV_192 PLL_AUDIO_MDIV_192 PLL_AUDIO_PEL_176 PLL_AUDIO_PEH_176 PLL_AUDIO_NDIV_176 PLL_AUDIO_XDIV_176 PLL_AUDIO_MDIV_176 PLL_SYSTEM_PEL_50 PLL_SYSTEM_PEH_50 PLL_SYSTEM_NDIV_50 PLL_SYSTEM_XDIV_50 PLL_SYSTEM_MDIV_50 PLL_SYSTEM_PEL_42_5 PLL_SYSTEM_PEH_42_5 PLL_SYSTEM_NDIV_42_5 PLL_SYSTEM_XDIV_42_5 PLL_SYSTEM_MDIV_42_5 OUTPUT_CONF PCM_DIV PCM_CONF PCM_CROSS OUTPUT_CONF GPSO_CONF INPUT_CONF I_AUDIO_CONFIG_1 I_AUDIO_CONFIG_2 I_AUDIO_CONFIG_3 Name Type RO RO RO RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW When DWT DWT DWT DEC DEC DEC DEC DEC DEC DEC DEC DEC DEC DEC DEC DEC DEC DEC DEC DEC DEC DEC DEC DEC DEC DEC DEC DEC DEC DEC DEC DEC DEC
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Register function CDBSA_CONFIGURATION Hex 0x5A 0x5B 0x5C 0x5D 0x5E 0x5F 0x60 0x61 0x62 0x63 0x64 0x65 BSB_CONFIGURATION 0x59 0x5A 0x5B CD_CONFIGURATION 0x40 0x41 0x42 0x43 0x44 0x46 0x47 0x48 0x49 0x4A 0x4B 0x4C 0x4D 0x4E Dec 90 91 92 93 94 95 96 97 98 99 100 101 89 90 91 64 65 66 67 68 70 71 72 73 74 75 76 77 78 Name INPUT_CONF I_AUDIO_CONFIG_1 I_AUDIO_CONFIG_2 I_AUDIO_CONFIG_3 I_AUDIO_CONFIG_4 I_AUDIO_CONFIG_5 I_AUDIO_CONFIG_6 I_AUDIO_CONFIG_7 I_AUDIO_CONFIG_8 I_AUDIO_CONFIG_9 I_AUDIO_CONFIG_10 I_AUDIO_CONFIG_11 POL_REQ INPUT_CONF I_AUDIO_CONFIG_1 BASIC_COMMAND FAST_FUNCTIO N_VAL REQUIRED_TRACK REQUIRED_DIR PLAY_MODE TYPE _CD_EXT_REQ MINUTE_REQ SECOND_REQ SECTOR_REQ MINUTE_SPENT SECOND_SPENT SCANNING_TIME PLAY_LIST_INDEX PLAY_LIST_VALUE Type RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW WO RW RW RW RW RO RO RO RO RO RO RW RW RW When DEC DEC DEC DEC DEC DEC DEC DEC DEC DEC DEC DEC DEC DEC DEC AEC ABO ABO ABO ABO AEC AEC AEC AEC AEC AEC ABO ABO ABO
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Register function Hex 0x86 0x87 0x88 0x89 0x8A 0x8B 0x8C 0x8D 0x8E 0x8F 0x90 0x91 0x92 0x93 0x94 0x95 0x96 0x97 0x98 0x99 0x9A 0x9B 0x9C 0x9D 0x9E 0x9F 0xA0 0xA1 0xA2 0xA3 0xA4 0xA5 0xA6 Dec 134 135 136 137 138 139 140 141 142 143 144 145 146 147 148 149 150 151 152 153 154 155 156 157 158 159 160 161 162 163 164 165 166 Name CD_SONG_INFO_C1 CD_SONG_INFO_C2 CD_SONG_INFO_C3 CD_SONG_INFO_C4 CD_SONG_INFO_C5 CD_SONG_INFO_C6 CD_SONG_INFO_C7 CD_SONG_INFO_C8 CD_SONG_INFO_C9 CD_SONG_INFO_C10 CD_SONG_INFO_C11 CD_SONG_INFO_C12 CD_SONG_INFO_C13 CD_SONG_INFO_C14 CD_SONG_INFO_C15 CD_SONG_INFO_C16 CD_SONG_INFO_C17 CD_SONG_INFO_C18 CD_SONG_INFO_C19 CD_SONG_INFO_C20 CD_SONG_INFO_C21 CD_SONG_INFO_C22 CD_SONG_INFO_C23 CD_SONG_INFO_C24 CD_SONG_INFO_C25 CD_SONG_INFO_C26 CD_SONG_INFO_C27 CD_SONG_INFO_C28 CD_SONG_INFO_C29 CD_SONG_INFO_C30 CD_SONG_INFO_C31 CD_SONG_INFO_C32 CD_SONG_TYPE_INFO Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO When AEC AEC AEC AEC AEC AEC AEC AEC AEC AEC AEC AEC AEC AEC AEC AEC AEC AEC AEC AEC AEC AEC AEC AEC AEC AEC AEC AEC AEC AEC AEC AEC AEC
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Register function Hex 0xA7 0xA8 0xA9 0xAA 0xAB 0xAC 0xAD 0xAE 0xAF 0xB0 0xB1 0xB2 0xB3 0xB4 0xB5 0xB6 0xB7 0xB8 0xB9 0xBA 0xBC COMMAND 0x10 0x3A 0x55 0x56 0x52 0x53 0x57 0x58 Dec 167 168 169 170 171 172 173 174 175 176 177 178 179 180 181 182 183 184 185 186 188 16 58 85 86 82 83 87 88 Name NB_OF_CUR_TRACK NB_OF_CUR_DIR CD_CUR_STATUS CD_TRACK_FORMAT CD_NB_OF_SUB_DIR CD_NB_OF_SUB_FILE DIRECTORY_LEVEL DIR_IDENTIFI ER_B1 DIR_IDENTIFI ER_B2 DIR_IDENTIFI ER_B3 DIR_IDENTIFI ER_B4 VOL_IDENTIFIER_B1 VOL_IDENTIFIER_B2 VOL_IDENTIFIER_B3 VOL_IDENTIFIER_B4 EXTRACT_BYTE_IDX_B1 EXTRACT_BYTE_IDX_B2 EXTRACT_BYTE_IDX_B3 EXTRACT_BYTE_IDX_B4 EXTRACT_ADR_MODE CONFIG_MODULE SOFT_RESET CK_CMD DEC_SEL RUN CRC_IGNORE MUTE SKIP PAUSE Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RW RW RW RW RW RW WO WO RW RW RW RW RW RW When AEC AEC AEC AEC AEC AEC AEC AEC AEC AEC AEC AEC AEC AEC AEC ABO ABO ABO ABO ABO DEC DWT DBO DEC DEC ABO ABO ABO ABO
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Register function STATUS Hex 0xCC 0xCD 0xCE 0x6F 0xD4 0xD5 0xD6 0xD7 0xD8 0xD9 BYPASSA_CONFIGURATION 0x70 0x71 0xCB MP3_CONFIGURATION 0x52 0x6B 0x6C 0x6D ADPCM_CONFIGURATION 0x70 0x71 0x72 0x73 0x74 MIX_CONFIGURATION 0x75 0x76 0x77 0x78 0x79 TONE_CONFIGURATION 0x7A 0x7B 0x7C 0x7D 0x7E 0x7F Dec 204 205 206 111 212 213 214 215 216 217 112 113 203 82 107 108 109 112 113 114 115 116 117 118 119 120 121 122 123 124 125 126 127 Name STATUS_MODE STATUS_CHAN_NB STATUS_SF STATUS_FE HEADER_1 HEADER_2 HEADER_3 HEADER_4 HEADER_5 HEADER_6 CHAN_NB SAMPLING_FREQ PCMCLK_INPUT CRC_IGNORE ERR_DEC_LEVEL ERR_DEC_NB_1 ERR_DEC_NB_2 CHAN_NB SAMPLING_FREQ ENC_STATE_REPEAT ENC_CODEC ENC_FRAME_LEN MIX_MODE MIX_DLA MIX_DLB MIX_DRA MIX_DRB TONE_ON TONE_FCUTH TONE_FCUTL TONE_GAINH TONE_GAINL TONE_GAIN_ATTEN Type RO RO RO RO RO RO RO RO RO RO RW RW RW RW RO RO RO RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW When EDF EDF EDF EDF EDF EDF EDF EDF EDF EDF DEC DEC DEC ABO EDB EDB EDB DEC DEC DEC DEC DEC ABO ABO ABO ABO ABO ABO ABO ABO ABO ABO ABO
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3 REGISTER DESCRIPTION 3.2 PLL_AUDIO_CONFIGURATION registers description
PLL_AUDIO_PEL_192 :
b7 b5 b4 b3 b2 b1 b0 b6 b5 b4 b3 b2 b1 b0
3.1 VERSION registers description
VERSION :
b7 b6
Address : 0xDC (220) Type : RW - DEC Software Reset : 58 Description : This register must contain a PEL value that enables the audio PLL to generate a frequency of ofact*192 kHz for the PCMCK.See table 1, 2 & 3. ofact is the oversampling factor needed by the DAC (ofac==246 or ofac==384). Default value at soft reset assume : - ofact == 256
Address : 0x00 (0) Type : RO - DWT Software Reset : 0x10 Hardware Reset : 0x10 Description : The VERSION register is Read-only and it is used to identify the IC on the application board.
IDENT :
b7 1 b6 0 b5 1 b4 0 b3 1 b2 1 b1 0 b0 0
- external crystal provide a CRYCK running at 14.31818 MHz
PLL_AUDIO_PEH_192 :
b7 b6 b5 b4 b3 b2 b1 b0
Address : 0x01 (1) Type : RO - DWT Software Reset : 0xAC Hardware Reset : 0xAC Description : IDENT is a read-only register and it is used to identify the IC on an application board. IDENT always has the value 0xAC.
SOFT_VERSION :
b7 b6 b5 b4 b3 b2 b1 b0
Address : 0xDD (221) Type : RW - DEC Software Reset : 187 Description : This register must contain a PEH value that enables the audio PLL to generate a frequency of ofact*192 kHz for the PCMCK.See table 1, 2 & 3. Default value at soft reset assume : - ofact == 256
Address : 0xD3 (211) Type : RO - DWT Software Reset : X
- external crystal provide a CRYCK running at 14.31818 MHz
PLL_AUDIO_NDIV_192 :
Description : The SOFT_VERSION register is Read-only and it is used to identify the software running on the IC.
b7
b6
b5
b4
b3
b2
b1
b0
Address : 0xDE (222) Type : RW - DEC Software Reset : 0
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Description : This register must contain a NDIV value that enables the audio PLL to generate a frequency of ofact*192 kHz for the PCMCK.See table 1, 2 & 3. Default value at soft reset assume : - ofact == 256 Address : 0xE1 (225) Type : RW - DEC Software Reset : 54 Description : This register must contain a PEL value that enables the audio PLL to generate a frequency of ofact*176 kHz for the PCMCK.See table 1, 2 & 3. Default value at soft reset assume : - fact == 256
b3 b2 b1 b0
- external crystal provide a CRYCK running at 14.31818 MHz
PLL_AUDIO_XDIV_192 :
b7 b6 b5 b4
- external crystal provide a CRYCK running at 14.31818 MHz
PLL_AUDIO_PEH_176 :
b7 b6 b5 b4 b3 b2 b1 b0
Address : 0xDF (223) Type : RW - DEC Software Reset : 3 Description : This register must contain a XDIV value that enables the audio PLL to generate a frequency of ofact*192 kHz for the PCMCK.See table 1, 2 & 3. Default value at soft reset assume : - ofact == 256
Address : 0xE2 (226) Type : RW - DEC Software Reset : 118 Description : This register must contain a PEH value that enables the audio PLL to generate a frequency of ofact*176 kHz for the PCMCK.See table 1, 2 & 3. Default value at soft reset assume : - ofact == 256
b3 b2 b1 b0
- external crystal provide a CRYCK running at 14.31818 MHz
PLL_AUDIO_MDIV_192 :
b7 b6 b5 b4
- external crystal provide a CRYCK running at 14.31818 MHz
PLL_AUDIO_NDIV_176 :
b7 b6 b5 b4 b3 b2 b1 b0
Address : 0xE0 (224) Type : RW - DEC Software Reset : 12 Description : This register must contain a MDIV value that enables the audio PLL to generate a frequency of ofact*192 kHz for the PCMCK.See table 1, 2 & 3. Default value at soft reset assume : - ofact == 256
Address : 0xE3 (227) Type : RW - DEC Software Reset : 0 Description : This register must contain a NDIV value that enables the audio PLL to generate a frequency of ofact*176 kHz for the PCMCK.See table 1, 2 & 3. Default value at soft reset assume : - ofact == 256
b3 b2 b1 b0
- external crystal provide a CRYCK running at 14.31818 MHz
PLL_AUDIO_PEL_176 :
b7 b6 b5 b4
- external crystal provide a CRYCK running at 14.31818 MHz
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PLL_AUDIO_XDIV_176 :
b7 b6 b5 b4 b3 b2 b1 b0
Description : This register must contain a PEL value that enables the system PLL to generate a frequency of 50 MHz for the SYSCK. See table 4. Default value at soft reset assume : - external crystal provide a CRYCK running at 14.31818 MHz
PLL_SYSTEM_PEH_50 :
b7 b6 b5 b4 b3 b2 b1 b0
Address : 0xE4 (228) Type : RW - DEC Software Reset : 2 Description : This register must contain a XDIV value that enables the audio PLL to generate a frequency of ofact*176 kHz for the PCMCK.See table 1, 2 & 3. Default value at soft reset assume : - ofact == 256
Address : 0xE7 (231) Type : RW - DEC Software Reset : 0 Description :
- external crystal provide a CRYCK running at 14.31818 MHz
PLL_AUDIO_MDIV_176 :
b7 b6 b5 b4 b3 b2 b1 b0
This register must contain a PEH value that enables the system PLL to generate a frequency of 50 MHz for the SYSCK. See table 4. Default value at soft reset assume : - external crystal provide a CRYCK running at 14.31818 MHz
PLL_SYSTEM_NDIV_50 :
Address : 0xE5 (229) Type : RW - DEC Software Reset : 8 Description : This register must contain a MDIV value that enables the audio PLL to generate a frequency of ofact*176 kHz for the PCMCK.See table 1,2 & 3. Default value at soft reset assume : - ofact == 256
b7
b6
b5
b4
b3
b2
b1
b0
Address : 0xE8 (232) Type : RW - DEC Software Reset : 0 Description : This register must contain a NDIV value that enables the system PLL to generate a frequency of 50 MHz for the SYSCK. See table 4. Default value at soft reset assume : - external crystal provide a CRYCK running at 14.31818 MHz
PLL_SYSTEM_XDIV_50 :
b7 b6 b5 b4 b3 b2 b1 b0
- external crystal provide a CRYCK running at 14.31818 MHz
PLL_SYSTEM_CONFIGURATION registers description PLL_SYSTEM_PEL_50 :
b7 b6 b5 b4 b3 b2 b1 b0
Address : 0xE6 (230) Type : RW - DEC Software Reset : 0
Address : 0xE9 (233) Type : RW - DEC Software Reset : 1
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STA016T
Description : This register must contain a XDIV value that enables the system PLL to generate a frequency of 50 MHZ for the SYSCK. See table 4. Default value at soft reset assume : - external crystal provide a CRYCK running at 14.31818 MHz
PLL_SYSTEM_MDIV_50 :
b7 b6 b5 b4 b3 b2 b1 b0
Description : This register must contain a PEH value that enables the system PLL to generate a frequency of 42.5 MHz for the SYSCK.See table 4. Default value at soft reset assume : - external crystal provide a CRYCK running at 14.31818 MHz
PLL_SYSTEM_NDIV_42_5 :
b7 b6 b5 b4 b3 b2 b1 b0
Address : 0xEA (234) Type : RW - DEC Software Reset : 13 Description : This register must contain a MDIV value that enables the system PLL to generate a frequency of 50 MHz for the SYSCK. See table 4. Default value at soft reset assume : - external crystal provide a CRYCK running at 14.31818 MHz
PLL_SYSTEM_PEL_42_5
b7 b6 b5 b4 b3 b2 b1 b0
Address : 0xE8 (232) Type : RW - DEC Software Reset : 0 Description : This register must contain a NDIV value that enables the system PLL to generate a frequency of 42.5 MHz for the SYSCK.See table 4. Default value at soft reset assume : - external crystal provide a CRYCK running at 14.31818 MHz
PLL_SYSTEM_XDIV_42_5 :
b7 b6 b5 b4 b3 b2 b1 b0
Address : 0xE6 (230) Type : RW - DEC Software Reset : 126 Description : This register must contain a PEL value that enables the system PLL to generate a frequency of 42.5 MHz for the SYSCK.See table 4. Default value at soft reset assume : - external crystal provide a CRYCK running at 14.31818 MHz
PLL_SYSTEM_PEH_42_5 :
b7 b6 b5 b4 b3 b2 b1 b0
Address : 0xE9 (233) Type : RW - DEC Software Reset : 1 Description : This register must contain a XDIV value that enables the system PLL to generate a frequency of 42.5 MHz for the SYSCK.See table 4. Default value at soft reset assume : - external crystal provide a CRYCK running at 14.31818 MHz
PLL_SYSTEM_MDIV_42_5 :
b7 b6 b5 b4 b3 b2 b1 b0
Address : 0xE7 (231) Type : RW - DEC Software Reset : 223
Address : 0xEA (234) Type : RW - DEC Software Reset : 10
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STA016T
Description : This register must contain a MDIV value that enables the system PLL to generate a frequency of 42.5 MHz for the SYSCK.See table 4. Default value at soft reset assume : - external crystal provide a CRYCK running at 14.31818 MHz
PCM_CONF :
b7 0 b6 CO6 b5 CO5 b4 CO4 b3 CO3 b2 CO2 b1 CO1 b0 CO0
Address : 0x68 (104) Type : RW - DEC Software Reset : 0
3.3 I2Sout_CONFIGURATION registers description
OUTPUT_CONF :
b7 b6 b5 b4 b3 b2 b1 b0
Description : If OUTPUT_CONF == 1, configure the I2Sout interface according following table.
Bit fields CO[1:0] 0 1 2 3 CO2 : : : : 16 18 20 24 Comment bits mode (16 slots bits mode (18 slots bits mode (20 slots bits mode (24 slots transmitted). transmitted). transmitted). transmitted).
Address : 0x66 (102) Type : RW - DEC Software Reset : 0 Description : If set to 1 enable the configurability of the PCMBLOCK Output thanks to following registers, else disable this configurability and take embedded default configuration for PCM-BLOCK registers. Note that this embedded default configuration can be retrieved by user thanks to following setting : - PCM_DIV = 3;
Polarity of BCKO : 0 : data are sent on the falling edge & stable on the rising). 1 : (data are sent on the rising edge & stable on the falling). 0 : I2S format is selected 1 : other format is selected Polarity of LRCKO : 0 : low->right, high->left). 1 : low->left, high->right so compliant to I2S format ). 0 : data are in the last BCKO cycles of LRCKO (right aligned data). 1 : data are in the first BCKO cycles of LRCKO (left aligned data). 0 : the transmission is LS bit first. 1 : the transmission is MS bit first.
CO3 CO4
- PCM_CONF = 0; - PCM_CROSS = 0;
CO5
PCM_DIV :
b7 0 b6 0 b5 DV5 b4 DV4 b3 DV3 b2 DV2 b1 DV1 b0 DV0 CO6
Address : 0x67 (103) Type : RW - DEC Software Reset : 0 Description : If OUTPUT_CONF== 1, configure the divider to generate the bit clock of the I2Sout interface, called BCK0, from PCMCK. according the following relation : BCKO = PCMCK / 2 * (PCM_DIV+1)
PCM_CROSS :
b7 0 b6 0 b5 0 b4 0 b3 0 b2 0 b1 CR1 b0 CR0
Address : 0x69 (105) Type : RW - DEC Software Reset : 0
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STA016T
Description : If OUTPUT_CONF == 1, CR[1:0] is used to configure the output crossbar according following table.
CR1 0 CR0 0 Comment Left channel is mapped on the left output. Right channel is mapped on the right output. Left channel is duplicated on both output channels. Right channel is duplicated on both output channels. Right and left channels are toggled.
GPSO_CONF :
b7 CF7 b6 CF6 b5 CF5 b4 CF4 b3 CF3 b2 CF2 b1 CF1 b0 CF0
Address : 0x6A (106) Type : RW - DEC Software Reset : 0 Description : If OUTPUT_CONF == 1, this register configure the GPSO interface.
Bit fields CF0 Comment Polarity of GPSO_CK : 0 : data provided on rising edge & stable on falling edge 1 : data provided on falling edge & stable on rising edge Polarity of GPSO_REQ : 0 : data are valid when GPSO_REQ is high 1 : data are valid when GPSO_REQ is low Reserved : to be set to 0.
0 1 1
1 0 1
3.4 GPSO_CONFIGURATION registers description
OUTPUT_CONF :
b7 X b6 X b5 X b4 X b3 X b2 0C2 b1 OC1 b0 OC0 CF[7:2] CF1
Address : 0x66 (102) Type : RW - DEC Software Reset : 0 Description :
Bit fields OC0 Comment Configuration of gpso : 0 : take embedded default configuration. 1 : configure gpso from register GPSO_CONF. Use of block PCM to generate clocks (PCMCK, LRCK & BCK): 0 : no use. 1 : use it. Configuration of PCM block: 0 : take embedded default configuration. 1 : configure PCM block from PCM_DIV & PCM_CONF registers.
3.5 I2Sin_CONFIGURATION registers description
INPUT_CONF :
b7 b6 b5 b4 b3 b2 b1 b0
Address : 0x5A (90) Type : RW - DEC Software Reset : 0 Description : If set to 1 enable the configurability of the I2Sin Input thanks to following registers, else disable this configurability and take embedded default configuration for I2Sin registers. Note that this embedded default configuration can be retrieved by user thanks to following setting : - I_AUDIO_CONFIG_1 = b00000110;
OC1
OC2
Note that embedded default configuration for GPSO can be retrieved by user thanks to following setting : - GPSO_CONF = b00000011; Note that embedded default configuration for PCM block is described at previous chapter.
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- I_AUDIO_CONFIG_2 = b11100000; - I_AUDIO_CONFIG_3 = b00000001;
STA016T
I_AUDIO_CONFIG_1:
b7 CF7 b6 CF6 b5 CF5 b4 CF4 b3 CF3 b2 CF2 b1 CF1 b0 CF0
Address : 0x5C (92) Type : RW - DEC Software Reset : 0 Description : See I_AUDIO_CONFIG_3 register description..
Address : 0x5B (91) Type : RW - DEC Software Reset : 0 Description : If INPUT_CONF == 1, this register configure the I2Sin interface.
Bit fields CF0 Comment Relative synchro : 0 : synchro with first data bit 1 : synchro one bit before first data bit Data reception configuration : 0 : LSB first 1 : MSB first Polarity of bit clock BCK : 0 : data provided on falling edge & stable on rising edge. 1 : data provided on rising edge & stable on falling edge Polarity of LR clock LRCK : 0 : negative 1 : positive Start value of LRCK : combined with CF3, this bit enable user to determine left/right couple according to the following table. Reserved : to be set to 0. CF4 0 0 1 1 Left/Right couples (data1/data2), (data3/data4),... (data0/data1), (data2/data3),... (data0/data1), (data2/data3),... (data1/data2), (data3/data4),...
I_AUDIO_CONFIG_3 :
b7 0 b6 0 b5 0 b4 0 b3 0 b2 0 b1 LR9 b0 LR8
Address : 0x5D (93) Type : RW - DEC Software Reset : 0 Description : If INPUT_CONF == 1, this register is used to configure the phase of the LRCK of the I2Sin.
Bit fields LR[4:0] Comment Position of the data within the LRCK phase : - if CF1 = 0 (LSB), value must be set to[31 - SL[9:5] - bit position of the first bit of data within the LRCK phase]. - if CF1 = 1 (MSB), value must be set to bit position of the first bit of data within the LRCK phase. Note that range of value for this bit position is [0:31]. Length-1 of the data. Max value is 31. Reserved : to be set to 0
CF1
CF2
CF3
CF4
CF[7:5] CF3 0 1 0 1
LR[9:5] LR[15:10]
3.6 CDBSA_CONFIGURATION registers description
INPUT_CONF :
b7 b6 b5 b4 b3 b2 b1 b0
I_AUDIO_CONFIG_2 :
b7 LR7 b6 LR6 b5 LR5 b4 LR4 b3 LR3 b2 LR2 b1 LR1 b0 LR0
Address : 0x5A (90) Type : RW - DEC Software Reset : 0
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STA016T
Description : If set to 1 enable the configurability of the CD & BS input interfaces in audio mode thanks to following registers, else disable this configurability and take embedded default configuration. Note that this embedded default configuration can be retrieved by user thanks to following setting : - I_AUDIO_CONFIG1 = b00010010; // clocks in input // & polarity negative
Bit CF0 CF1 CF2 Comment Reserved : to be set to 0 Reserved : to be set to 1 Direction of bit clocks CD_BCK & BS_BCK: 0 : input 1 : output Polarity of bit clocks CD_BCK & BS_BCK : 0 : data provided on falling edge & stable on rising edge 1 : data provided on rising edge & stable on falling edge Reserved : to be set to 1 Direction of LR clocks CD_LRCK & BS_LRCK : 0 : input 1 : output Polarity of LR clocks CD_LRCK & BS_LRCK : 0 : left sample corresponds to the low level phase of LRCK 1 : left sample corresponds to the high level phase of LRCK Reserved : to be set to 0
CF3
- I_AUDIO_CONFIG2 = b00110010; // synchro with first data bit // data unsigned, MSB first - I_AUDIO_CONFIG3 = b11001111; // LRCK phase length is 1 - I_AUDIO_CONFIG4 = b00000011; // LRCK phase length is 16 - I_AUDIO_CONFIG5 = 0xFF; // received 16 bits - I_AUDIO_CONFIG6 = 0xFF; // received 16 bits - I_AUDIO_CONFIG7 = 0x00; // received 16 bits - I_AUDIO_CONFIG8 = 0x00; // received 16 bits - I_AUDIO_CONFIG9 = 16; // data size is 16 - I_AUDIO_CONFIG10 = 0x00; // no use because clock in input - I_AUDIO_CONFIG11 = 0x00; // no use because clock in input
CF4 CF5
CF6
CF7
I_AUDIO_CONFIG_2 :
b7 b6 b5 b4 b3 b2 b1 b0 CF8
CF15 CF14 CF13 CF12 CF11 CF10 CF9
Address : 0x5C (92) Type : RW - DEC Software Reset : 0 Description :
_AUDIO_CONFIG_1 :
b7 CF7 b6 CF6 b5 CF5 b4 CF4 b3 CF3 b2 CF2 b1 CF1 b0
If INPUT_CONF == 1, this register is used to configurate CD & BS input interfaces in audio mode.
Bit CF0 CF8 Comment Relative synchro : 0 : synchro with first data bit 1 : synchro one bit before first data bit Data reception configuration : 0 : LSB first 1 : MSB first Arithmetic type of the reception : 0 : unsigned data 1 : signed data
Address : 0x5B (91) Type : RW - DEC Software Reset : 0 Description : If INPUT_CONF == 1, this register is used to configurate CD & BS input interfaces in audio mode.
CF10 CF9
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STA016T
Bit CF11 Comment Bit to select the reference clock used to generate BCK if clocks are in output (CF2=1 & CF5=1). Otherwise this bit is useless. 0 : SYSCK 1 : PCMCK Reserved : to be set to 1 Reserved : to be set to 1 Reserved : to be set to 0 Reserved : to be set to 0 Bit fields LR[11:6] Comment Length-1 of phase 2 of LR clocks CD_LRCK & BS_LRCK. Max value is 31. Reserved : to be set to 0
LR[15:12]
CF12 CF13 CF14 CF15
I_AUDIO_CONFIG_5:
b7 MA7 b6 MA6 b5 MA5 b4 MA4 b3 MA3 b2 MA2 b1 MA1 b0 MA0
Address : 0x5F (95) Type : RW - DEC
I_AUDIO_CONFIG_3 :
b7 LR7 b6 LR6 b5 LR5 b4 LR4 b3 LR3 b2 LR2 b1 LR1 b0 LR0
Software Reset : 0 Description : See I_AUDIO_CONFIG_8 register description.
Address : 0x5D (93) Type : RW - DEC Software Reset : 0 Description : See I_AUDIO_CONFIG_4 register description..
I_AUDIO_CONFIG_6 :
b7 b6 b5 b4 b3 b2 b1 b0 MA8
MA15 MA14 MA13 MA12 MA11 MA10 MA9
Address : 0x60 (96) Type : RW - DEC
I_AUDIO_CONFIG_4 :
b7 b6 b5 b4 b3 b2 b1 LR9 b0 LR8
Software Reset : 0 Description : See I_AUDIO_CONFIG_8 register description..
LR15 LR14 LR13 LR12 LR11 LR10
Address : 0x5E (94) Type : RW - DEC Software Reset : 0 Description : If INPUT_CONF == 1, this register is used to configurate LR clocks (CD_LRCK & BS_LRCK) of CD & BS input interfaces in audio mode.
Bit fields LR[5:0] Comment Length-1 of phase 1 of LR clocks CD_LRCK & BS_LRCK. Max value is 31.
I_AUDIO_CONFIG_7 :
b7 b6 b5 b4 b3 b2 b1 b0
MA23 MA22 MA21 MA20 MA19 MA18 MA17 MA16
Address : 0x61 (97) Type : RW - DEC Software Reset : 0 Description : See I_AUDIO_CONFIG_8 register description..
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STA016T
I_AUDIO_CONFIG_8 :
b7 b6 b5 b4 b3 b2 b1 b0
II_AUDIO_CONFIG_11 :
b7 b6 b5 b4 b3 b2 b1 b0 DV8
MA31 MA30 MA29 MA28 MA27 MA26 MA25 MA24
DV15 DV14 DV13 DV12 DV11 DV10 DV9
Address : 0x62 (98) Type : RW - DEC Software Reset : 0 Description : If INPUT_CONF == 1, those registers are used to configure the MASK to be appllied to CD_LRCK & BS_LRCK phase 1 & 2. - if MAi set to 0, then bit i of both phases is not received.
Address : 0x65 (101) Type : RW - DEC Software Reset : 0 Description : If INPUT_CONF == 1, those registers are used to create BCK if configurated in output (so if CF2=1 & CF5=1): then value of DV[15:0] is the divider factor to be applied to the selected clock (CF11 select either SYSCLK or PCMCLK) to create BCK. Note : value 0 & 1 correspond to a bypass of the dividers.
- if MAi set to 1, then bit i of both phases is received.
I_AUDIO_CONFIG_9 :
b7 DL7 b6 DL6 b5 DL5 b4 DL4 b3 DL3 b2 DL2 b1 DL1 b0 DL0
3.7 BSB_CONFIGURATION registers description
POL_REQ :
b7 b6 b5 b4 b3 b2 b1 b0
Address : 0x63 (99) Type : RW - DEC Software Reset : 0 Description : If INPUT_CONF == 1, this register is used to configurate the size of the data to be received by CD & BS input interfaces in audio mode. Max is 32.
Address : 0x59 (89) Type : WO - DEC Software Reset : 0 Description : This register manage the polarity of the data REQ signal DREQ of the BS input interface. If set to 0, data are requested when REQ = 0. If set to 1, data are requested when REQ = 1.
I_AUDIO_CONFIG_10 :
b7 DV7 b6 DV6 b5 DV5 b4 DV4 b3 DV3 b2 DV2 b1 DV1 b0
INPUT_CONF :
DV0 b7 b6 b5 b4 b3 b2 b1 b0
Address : 0x64 (100) Type : RW - DEC Software Reset : 0 Description : See I_AUDIO_CONFIG_11 register description.
Address : 0x5A (90) Type : RW - DEC Software Reset : 0 Description :
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STA016T
If set to 1 enable the configurability of the BSB input interfaces in burst mode thanks to following register, else disable this configurability and take embedded default configuration. Note that this embedded default configuration can be retrieved by user thanks to following setting : - I_AUDIO_CONFIG1 = b00000000;// polarity choice
Value 3 4 5 6 9 10 11 fast forward fast rewind track up track down directory down directory up play specified track set a play-list index edit play list play current dir play cd from beginning start playing music start searching bytes/mute navigation ID3 name of song required ID3 name of author required ID3 name of album required name of file required name of directory required Command
I_AUDIO_CONFIG_1 :
b7 0 b6 0 b5 0 b4 0 b3 0 b2 0 b1 0 b0 CF0
12 13 14 15 112 113 124 125
Address : 0x5B (91) Type : RW - DEC Software Reset : 0 Description : If INPUT_CONF == 1, this register is used to configure BSB bit clock.
Bit CF0 Comment Polarity of bit clock BS_BCK : 0 : data provided on falling edge & stable on rising edge. 1 : data provided on rising edge & stable on falling edge.
126 127 128
FAST_FUNCTIONAL_VAL :
b7 b6 b5 b4 b3 b2 b1 b0
Address : 0x41 (65) Type : RW - ABO
3.8 CD_CONFIGURATION registers description
BASIC_COMMAND :
b7 b6 b5 b4 b3 b2 b1 b0
Software Reset : 0 Description : This register specifies the volume of fast function. For the "fast forward function" it is a number between 1 and 20. For the "fast rewind function" it is a number of second
Address : 0x40 (64) Type : RW - AEC Software Reset : 0
REQUIRED_TRACK :
Description : Used for giving to dsp basic cd-player commands.
Value 1 2 Command stop playing music pause b7 b6 b5 b4 b3 b2 b1 b0
Address : 0x42 (66) Type : RW - ABO Software Reset : 0
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STA016T
Description : This specifies the number of track to play.
TYPE_CD_EXT_REQ:
b7 b6 b5 b4 b3 b2 b1 b0
Address : 0x46 (70)
REQUIRED_DIR :
b7 b6 b5 b4 b3 b2 b1 b0
Type : RO - AEC Software Reset : 0 Description : This register specifies the type of request sent to the cd module.
Value 10 18 20 Signific ation application is in pause after EOT or EOD request for a sector begin of track reached ready to receive a new command dsp ready to run cd application stopped. time spent on track available request for root song information available
Address : 0x43 (67) Type : RW - ABO Software Reset : 0 Description : This register specifies the number of directory to play.
PLAY_MODE :
b7 b6 b5 b4 b3 b2 b1 b0
30 35 40 66 112 120
Address : 0x44 (68) Type : RW - ABO Software Reset : 0 Description : This register specifies the playing mode.
Bit [1:0] Mode end of directory: 0: play next directory 1: replay same directory 2: make pause. other: reserved end of track: 0: play next track. 1: replay same track. 2: make pause. other: reserved next track choice: 0: linear mode. 1: random mode. playing time for track: 0: until end of track. 1: scanning mode. end of CD: 0: stop. 1: replay same CD..
MINUTE_REQ :
b7 b6 b5 b4 b3 b2 b1 b0
Address : 0x47 (71) Type : RO - AEC Software Reset : 0 Description : This register specifies to the CD module the minute location requested.
[3:2]
4
5
SECOND_REQ :
b7 b6 b5 b4 b3 b2 b1 b0
6
Address : 0x48 (72) Type : RO - AEC
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STA016T
Software Reset : 0 Description : This register specifies to the CD module the second location requested.
SCANNING_TIME :
b7 b6 b5 b4 b3 b2 b1 b0
Address : 0x4C (76) Type : RW - ABO Software Reset : 0
SECTOR_REQ :
b7 b6 b5 b4 b3 b2 b1 b0
Description : This register specifies in second (<60) the playing time for each track in scanning mode.
Address : 0x49 (73) Type : RO - AEC Software Reset : 0 Description : This register specifies to the CD module the sector location requested.
PLAY_LIST_INDEX:
b7 b6 b5 b4 b3 b2 b1 b0
Address : 0x4D (77) Type : RW - ABO Software Reset : 0
MINUTE_SPENT :
b7 b6 b5 b4 b3 b2 b1 b0
Description : This register specifies the index in the play list of the song to enter in the play list, it is also a value between 1 and the maximum number of track in the directory.
Address : 0x4A (74) Type : RO - AEC Software Reset : 0 Description : This register specifies the number of minute spent from the beginning of the track. It is reset at the beginning of a new track.
PLAY_LIST_VALUE:
b7 b6 b5 b4 b3 b2 b1 b0
Address : 0x4E (78) Type : RW - ABO Software Reset : 0
SECOND_SPENT :
b7 b6 b5 b4 b3 b2 b1 b0
Description : This register specifies the song index in the directory to enter in the play list, it is also a value between 1 and the maximum number of track in the directory.
Address : 0x4B (75) Type : RO - AEC Software Reset : 0
CD_SONG_INFO_Cn :
Description : This register specifies the number of second spent from the beginning of the track. It is resected at the beginning of a new track.
b7
b6
b5
b4
b3
b2
b1
b0
Address : 0x86 (134) to 0xA5 (165) Type : RO - AEC Software Reset : 0
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STA016T
Description : This register contains the n th character of the song info required (ASCII code).
NB_OF_CUR_DIR :
b7 b6 b5 b4 b3 b2 b1 b0
Address : 0xA8 (168) Type : RO - AEC
CD_SONG_TYPE_INFO :
b7 b6 b5 b4 b3 b2 b1 b0
Software Reset : 0 Description : This register specifies the number of the current directory into the CD: from 1 to max number of directory. This number is negative if going backward to the end of the CD with the command directory-down.
Address : 0xA6 (166) Type : RO - AEC Software Reset : 0 Description : This register specifies the kind of current information contained in the
Value 0 1 2 3 4 5 6 7 Signification information not valid ID3 song name information ID3 author name information ID3 album name information file name information directory name information bytes requested play list content
CD_CUR_STATUS :
b7 b6 b5 b4 b3 b2 b1 b0
Address : 0xA9 (169) Type : RO - ABO Software Reset : 0 Description : This register gives the status of the CD application.
Bit 0 1 2 3 Mode 0: unknown format. 1: recognized format reserved. 0: searching track. 1: track founded. 0: ID3 present. 1: ID3 missing. 0: no error detected. 1: error detected. 0: CD application in pause. 1: CD application not in pause. 0: CD not playable. 1: CD playable. 0: music mode. 1: searching bytes mode
When the track has changed the previous information are declared "not valid". New valid information should be requested by user.
NB_OF_CUR_TRACK :
b7 b6 b5 b4 b3 b2 b1 b0
4 5 6 7
Address : 0xA7 (167) Type : RO - AEC Software Reset : 0 Description : This register specifies the number of the current track into his directory (sub-directories included): from 1 to max number of track/subdirectory.
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STA016T
CD_TRACK_FORMAT :
b7 b6 b5 b4 b3 b2 b1 b0
Description : This register specifies the number of file in the current directory.
Address : 0xAA (170) Type : RO - AEC Software Reset : 0 Description : This register specifies the format of the played track considering the extension name. Only 1 bit can be set in the same time:
Bit 0 1 2 3 4 FORMAT
DIRECTORY_LEVEL :
b7 b6 b5 b4 b3 b2 b1 b0
Address : 0xAD (173) Type : RO - AEC Software Reset : 0 Description :
0 : UNKNOWN 1 : MP3 1: RESERVED MPEG1 MPEG2 MPG
This register specifies the current directory level.
DIR_IDENTIFIER_Bn :
b7 b6 b5 b4 b3 b2 b1 b0
Address : 0xAE (174) to 0xB1 (177) Type : RO - AEC Software Reset : 0
NB_OF_SUBDIR :
b7 b6 b5 b4 b3 b2 b1 b0
Description : This register specifies the nth byte of the number of byte of the current directory. Considering that two directories have very few chance to have exactly the same number of byte, this number allows to identify the directory. The first byte (174) is the MSB and the last one (177) is the LSB.
Address : 0xAB (171) Type : RO - AEC Software Reset : 0 Description : This register specifies the number of sub-directory in the current directory.
VOL_IDENTIFIER_Bn:
Address : 0xB2 (178) to 0xB5 (181) Type : RO - AEC
NB_OF_SUB_TRACK :
b7 b6 b5 b4 b3 b2 b1 b0
Software Reset : 0 Description : This register specifies the nth byte of the number of byte of the CD. Considering that two CD have very few chance to have exactly the same number of byte, this number allows to identify the CD. The first byte (178) is the MSB and the last one (181) is the LSB.
Address : 0xAC (172) Type : RO - AEC Software Reset : 0
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STA016T
EXTRACT_BYTE_IDX_Bn:
b7 b6 b5 b4 b3 b2 b1 b0
Bit 1
FORMAT 0: ID3 tag not checked 1: ID3 tag checked reference for counting sector in minute.
Address : 0xB6 (182) to 0xB8 (185) Type : RW - ABO Software Reset : 0 Description : This register specifies the nth byte of the index of the byte block to extract from the CD. This number should be relative to the beginning of the track containing these bytes.
other
3.9 COMMAND registers description
SOFT_RESET :
b7 b6 b5 b4 b3 b2 b1 b0
Address : 0x10 (16)
EXTRACT_ADR_MODE :
b7 b6 b5 b4 b3 b2 b1 b0
Type : WO - DWT Software Reset : 0 Description : When user write 1 in this register, a soft reset occurs. The core command register and the interrupt register are cleared. The decoder goes into idle mode.
Address : 0xBA (186) Type : RW - ABO Software Reset : 0 Description : This register specifies addressing mode type for byte extraction: if set to 0, it is a relative (to the beginning of the current file) addressing mode, if set to 1 it is an absolute addressing mode (relative to the beginning of the CD).
CK_CMD :
b7 b6 b5 b4 b3 b2 b1 b0
Address : 0x3A (58) Type : WO - DBO Software Reset : 1
CD_CONFIG_MODULE :
b7 b6 b5 b4 b3 b2 b1 b0
Hardware Reset : 1 Description :
Address : 0xBC (188) Type : RO - ABO Software Reset : 0xA Description : This register set some parameters describing the way the module transmit the data to the DSP.
Bit 0 FORMAT 0: valid data byte swapped. 1: valid data not byte swapped.
After a soft reset, user must write 0 in CK_CMD to run the core clock of the chip. This will begin the boot of the chip, and so get it out of its idle state.
DEC_SEL :
b7 b6 b5 b4 b3 b2 b1 b0
Address : 0x55 (85) Type : RW - DEC Software Reset : 0
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STA016T
Description : This register select the decoding data flux according the mode written in following table.
Bit(7:0) 0 1 2 3 4 5 6 7 8 9 10 CD_MP3 CD_BYPASSA RESERVED BSB_MP3 BSB_ADPCM_DECODER RESERVED BSA_ADPCM_ENCODER BSA_BYPASSA I2Sin_ADPCM_ENC I2Sin_BYPASSA SINE (test mode chip alive) Mode
Address : 0x52 (82) Type : RW - ABO Software Reset : 0 Description : For decoders having CRC abilities (see each decoder configuration), if set to 0 enable the check of CRC, if set to 1 disable the check of the CRC.
MUTE :
b7 b6 b5 b4 b3 b2 b1 b0
Address : 0x53 (83) Type : RW - ABO Software Reset : 0 Description : For decoders having MUTE abilities (see each decoder configuration), if set to 0 disable the mute of the decoder, if set to 1 enable the mute of the decoder. Note that during a MUTE the input stream keeps on entering.
RUN :
b7 b6 b5 b4 b3 b2 b1 b0
Address : 0x56 (86) Type : RW - DEC Software Reset : 0
b7 b6 b5 b4 b3 b2 b1 b0
SKIP :
Description : - When a software reset occurs, register RUN is reset (value 0) by the dsp (see I).
Address : 0x57 (87) Type : RW - ABO Software Reset : 0 Description : For data flux using USSB Input, if SKIP == n>2, decoder skip (n-1) out of n frames. Note that maximum value for n is 8, and if n==0 or n==1, no frames is skipped.
- When boot routines are finished, the dsp write inside RUN register the value 2 : this is the start of the external configuration period (start of DEC : see I). - When the external device wants to end the external configuration period, it must write the value 1 inside the register RUN: this is the run command that starts the decoding process (see I).
PAUSE :
b7 b6 b5 b4 b3 b2 b1 b0
CRC_IGNORE :
Address : 0x58 (88)
b7 b6 b5 b4 b3 b2 b1 b0
Type : RW - ABO
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STA016T
Software Reset : 0 Description : For decoders having PAUSE abilities (see each decoder configuration), if set to 0 disable the pause of the decoder, if set to 1 enable the pause of the decoder. Note that during a PAUSE the input stream is stopped.
STATUS_CHANS_NB :
b7 b6 b5 b4 b3 b2 b1 b0
Address : 0xCD (205) Type : RO - EDF Software Reset : 0 Description :
3.10 STATUS registers description
STATUS_MODE :
b7 b6 b5 b4 b3 b2 b1 b0
This register gives the number of channel currently decoded.
STATUS_SF :
b7 b6 b5 b4 b3 b2 b1 b0
Address : 0xCC (204) Type : RO - EDF Software Reset : 0 Description : This register give the type of the currently decoded bitstream according following table.
Value 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 MP3 MP3_25 RESERVED RESERVED RESERVED ADPCM RESERVED BYPASS RESERVED RESERVED RESERVED MPG2 RESERVED RESERVED RESERVED RESERVED RESERVED RESERVED UNKNOWN Mode
Address : 0xCE (206) Type : RO - EDF Software Reset : 0 Description : This register gives the index of the sampling frequency of the stream currently decoded. Note that sampling frequency indexes are given by table 5
STATUS_FE :
b7 b6 b5 b4 b3 b2 b1 b0
Address : 0x6F (111) Type : RO - AEC Software Reset : 0 Description : This register give the status of the synchronization process according following table.
Value 0 1 2 3 Level Syncrho not started Syncword found Syncword search Syncword hard to find
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STA016T
HEADER _n:
b7 b6 b5 b4 b3 b2 b1 b0
Address : 0xCB (203) Type : RW - DEC Software Reset : 0 Description : If set to 1, the PCMCLK pad is configure as input in order to receive an external reference clock.
Address : 0xD4 (212) to 0xD9 (217) Type : RO - EDF Software Reset : 0 Description : This register give the nth byte of the header of the frame currently decoded
3.12 MP3_CONFIGURATION registers description
ERR_DEC_LEVEL :
3.11 BYPASSA_CONFIGURATION registers description
CHAN_NB :
b7 b6 b5 b4 b3 b2 b1 b0
b7
b6
b5
b4
b3
b2
b1
b0
Address : 0x6B (107) Type : RO - EDF Software Reset : 0 Description : This register give the status of the mp3 decoding process according the error level written in following table.
Value 0 1 2 No error Warning while decoding Error while decoding Fatal error while decoding Level
Address : 0x70 (112) Type : RW - DEC Software Reset : 0 Description : User must specify the number of channel for bypassa decoder to decode.
SAMPLING_FREQ: :
b7 b6 b5 b4 b3 b2 b1 b0
3
Address : 0x71 (113) Type : RW - DEC Software Reset : 0 Description : User must specify the sampling frequency of the stream to decode if clocks direction of the input interface is input. Sampling frequency index is given by table 4.
ERR_DEC_NB_1 :
b7 ER7 b6 ER6 b5 ER5 b4 ER4 b3 ER3 b2 ER2 b1 ER1 b0 ER0
Address : 0x6C (108) Type : RO - EDF Software Reset : 0 Description : See ERR_DEC_NB_2 register description.
PCMCLK_INPUT :
b7 b6 b5 b4 b3 b2 b1 b0
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STA016T
ERR_DEC_NB_2 :
b7 b6 b5 b4 b3 b2 b1 b0 ER8
Description : It allows the user to specify the number of channel of the stream to encode.
Value 1 2 5 Codec stream mono encoded as mono stream stereo encoded as stereo stream stereo encoded as mono with left channel. stream stereo encoded as mono with right channel.
ER15 ER14 ER13 ER12 ER11 ER10 ER9
Address : 0x6D (109) Type : RO - EDF Software Reset : 0 Description : This register give the status of the mp3 decoding process according the error number written in following table.
Event ER0 == 1 ER1 == 1 ER2 == 1 ER3 == 1 ER4 == 1 ER5 == 1 ER6 == 1 ER7 == 1 ER8 == 1 ER9 == 1 ER10 == 1 ER11 == 1 ER12 == 1 ER13 == 1 ER14 == 1 ER15 == 1 Comment crc_error cutoff_error big_value_error hufftable_error mod_buf_size_error huffman_decode_error dynpart_exchange_error gr_length_error input_bit_available_error ch_length_error head_framelength_error dynpart_length_error block_type_error head_emphasis_error head_samp_freq_error head_layer_error
9
stream mono stands for only 1 channel is transmitted, data are also not interleaved. Encode a stereo stream as mono reduce from an half the encoded data.
SAMPLING_FREQ. :
b7 b6 b5 b4 b3 b2 b1 b0
Address : 0x71 (113) Type : RW - DEC Software Reset : 0 Description : It allows the user to specify the sampling frequency of the stream to encode.See table 6 of sample frequencies.
ENC_STATE_REPEAT :
b7 b6 b5 b4 b3 b2 b1 b0
Address : 0x72 (114)
3.13 ADPCM_CONFIGURATION registers description
CHAN_NB :
b7 b6 b5 b4 b3 b2 b1 b0
Type : RW - DEC Software Reset : 0 Description : It allows the user to specify at which frequency the state of the encoder should be repeated in the stream :(1/HOST_ENC_STATE_REPEAT) frame.
Address : 0x70 (112) Type : RW - DEC Software Reset : 0
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STA016T
ENC_CODEC :
b7 b6 b5 b4 b3 b2 b1 b0
:
Value 0 1 2 3 Mode diseable mix/volume control volume control mono to stereo (up-mix) stereo to mono (down-mix)
Address : 0x73 (115) Type : RW - DEC Software Reset : 0 Description : It allows the user to specify the codec to use for the encoding:
Value 0 1 2 3 Intel/DVI G723_24 G721 G723_40 Codec
MIX_DLA:
b7 b6 b5 b4 b3 b2 b1 b0
Address : 0x76 (118) Type : RW - ABO Software Reset : 0 Description :
ENC_FRAME_LEN :
b7 b6 b5 b4 b3 b2 b1 b0
This register specifies the direct left attenuation (in dB).
Address : 0x74 (116) Type : RW - DEC Software Reset : 0 Description : It allows the user to specify the number of words by channel included in 1 frame: value from 1 to 15 (multiplied by 64 inside dsp).
MIX_DLB:
b7 b6 b5 b4 b3 b2 b1 b0
Address : 0x77 (119) Type : RW - ABO Software Reset : 0 Description :
3.14 MIX_CONFIGURATION registers description
MIX_MODE:
This register specifies the left attenuation (in dB) on rigth channel.
MIX_DRA:
b7 b6 b5 b4 b3 b2 b1 b0 b7 b6 b5 b4 b3 b2 b1 b0
Address : 0x75 (117) Type : RW - ABO Software Reset : 2 Description : This register selectes the mode of mix/volume control Description : This register specifies the direct right attenuation (in dB). Address : 0x78 (120) Type : RW - ABO Software Reset : 0
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STA016T
MIX_DRB:
b7 b6 b5 b4 b3 b2 b1 b0
Software Reset : 10 Description : This register specifies the low cut frequency: fcut(in Hz) = (TONE_FCUTL+1)*10
Address : 0x79(121) Type : RW - ABO Software Reset : 0 Description : This register specifies the rigth attenuation (in dB) on left channel.
TONE_GAINH :
b7 b6 b5 b4 b3 b2 b1 b0
Address : 0x7D(125) Type : RW - ABO
3.15 TONE_CONFIGURATION registers description
TONE_ON:
b7 b6 b5 b4 b3 b2 b1 b0
Software Reset : 12 Description : This register specifies the gain on high frequencies: gain(in Db)=(TONE_GAINH-12)*1.5
Address : 0x7A(122) Type : RW - ABO Software Reset : 0 Description : This register enables/diseables (1/0) the tone control.
TONE_GAINL :
b7 b6 b5 b4 b3 b2 b1 b0
Address : 0x7E(126) Type : RW - ABO Software Reset : 12
TONE_FCUTH :
b7 b6 b5 b4 b3 b2 b1 b0
Description : This register specifies the gain on high frequencies: gain (in Db)=(TONE_GAINL-12)*1.5. Value of register from 0 to 24.
Address : 0x7B(123) Type : RW - ABO Software Reset : 20 Description : This register specifies the high cut frequency: fcut(in Hz)=(TONE_FCUTH+1)*50.
TONE_GAIN_ATTEN :
b7 b6 b5 b4 b3 b2 b1 b0
Address : 0x7F(127) Type : RW - ABO
TONE_FCUTL :
b7 b6 b5 b4 b3 b2 b1 b0
Software Reset : 0 Description : This register specifies the attenuation on global spectrum: gain (in dB)=-TONE_GAIN_ATTEN*1.5. Value of register from 0 to 12.
Address : 0x7C(124) Type : RW - ABO
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STA016T
3.16 TABLES Table 2. values to configure audio PLL for ofact==256.
This table give values to configure the audio PLL according CRYCK so that to generate a PCMCK == 256*SF.
Register PLL_AUDIO_PEL_192 PLL_AUDIO_PEH_192 PLL_AUDIO_NDIV_192 PLL_AUDIO_XDIV_192 PLL_AUDIO_MDIV_192 PLL_AUDIO_PEL_176 PLL_AUDIO_PEH_176 PLL_AUDIO_NDIV_176 PLL_AUDIO_XDIV_176 PLL_AUDIO_MDIV_176 CRYCK in MHz 10 42 169 0 3 18 56 16 0 3 17 CRYCK in MHz 14.31818 58 187 0 3 12 54 118 0 2 8 CRYCK in MHz 14.7456 85 85 0 0 2 0 64 0 3 11
Table 3. values to configure audio PLL for ofact==384
This table give values to configure the audio PLL according CRYCK so that to generate a PCMCK == 384*SF.
Register PLL_AUDIO_PEL_192 PLL_AUDIO_PEH_192 PLL_AUDIO_NDIV_192 PLL_AUDIO_XDIV_192 PLL_AUDIO_MDIV_192 PLL_AUDIO_PEL_176 PLL_AUDIO_PEH_176 PLL_AUDIO_NDIV_176 PLL_AUDIO_XDIV_176 PLL_AUDIO_MDIV_176 CRYCK in MHz 10 224 190 0 1 13 42 140 0 1 12 CRYCK in MHz 14.31818 108 76 0 1 9 54 118 0 1 8 CRYCK in MHz 14.7456 0 0 0 1 9 0 48 0 1 8
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STA016T
Table 4. values to configure audio PLL for ofact==512.
This table give values to configure the audio PLL according CRYCK so that to generate a PCMCK == 512*SF.
Register PLL_AUDIO_PEL_192 PLL_AUDIO_PEH_192 PLL_AUDIO_NDIV_192 PLL_AUDIO_XDIV_192 PLL_AUDIO_MDIV_192 PLL_AUDIO_PEL_176 PLL_AUDIO_PEH_176 PLL_AUDIO_NDIV_176 PLL_AUDIO_XDIV_176 PLL_AUDIO_MDIV_176 CRYCK in MHz 10 42 169 0 1 18 56 16 0 1 17 CRYCK in MHz 14.31818 58 187 0 0 5 157 157 0 1 11 CRYCK in MHz 14.7456 85 85 0 1 12 0 64 0 1 11
Table 5. values to configure system PLL for SYSCK.
This table give values to configure the system PLL according CRYCK so that to generate a SYSCK == 50MHz. or SYSCK == 42.5MHz.
Register PLL_SYSTEM_PEL_50 PLL_SYSTEM_PEH_50 PLL_SYSTEM_NDIV_50 PLL_SYSTEM_XDIV_50 PLL_SYSTEM_MDIV_50 PLL_SYSTEM_PEL_42_5 PLL_SYSTEM_PEH_42_5 PLL_SYSTEM_NDIV_42_5 PLL_SYSTEM_XDIV_42_5 PLL_SYSTEM_MDIV_42_5 CRYCK in MHz 10 162 11 0 1 19 0 0 0 1 16 CRYCK in MHz 14.31818 0 0 0 1 13 126 223 0 1 10 CRYCK in MHz 14.7456 28 152 0 1 12 100 135 0 1 10
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STA016T
Table 6. index of the Sampling Frequency.
Index 0 1 2 4 5 6 8 9 10 12 13 14 16 17 18 3, 7, 11, 15 or 19 Frequency 48 kHz 44.1 kHz 32 kHz 96 kHz 88.2 kHz 64 kHz 24 kHz 22.05 kHz 16 kHz 12 kHz 11.025 kHz 8 kHz 192 kHz 176.4 kHz 128 kHz illegal frequency
3.17 NOTATIONS
ABO AEC BCK BSA BSB BS BYPASSA CD CK CRYCK DBO DEC DWT EDB EDF LRCK ofact PCMCK SF SYSCK X : After BOot (see I). : After External Config (see I). : Bit ClocK : BitStream input interface in Audio mode. : BitStream input interface in Burst mode. : BitStream input interface. : decoder BYPASS an Audio stream. : input interface for CD. : ClocK. : CRYstal ClocK provided to the chip by an external crystal. : During BOot (see I). : During External Config (see I). : During Whole Time (see I). : Every Decoded Block (see I). : Every Decoded Frame (see I). : Left Right ClocK for an I2S interface. : oversampling factor for PCMCK (PCMCK == ofact * SF). : PCM ClocK (can be generated by the audio PLL). : Sampling Frequency. : SYStem ClocK (clock of the core, can be generated by the system PLL). : don't care.
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STA016T
I/O CELL DESCRIPTION 1) TTL Tristate Output Pad Buffer, 3V capable 4mA, with Slew Rate Control
Pin numbers: 4, 18, 20, 21, 22, 25, 54, 56, 59
EN Z A
D98AU904
INPUT PIN Z
MAX LOAD 100pF
2) TTL Schmitt Trigger Bidir Pad Buffer, 3V capable, 4mA, with Slew Rate Control
Pin numbers: 1, 2, 3, 7, 8, 9, 19
EN IO A
INPUT PIN IO
CAPACITANCE TBD
OUTPUT PIN IO
MAX LOAD 100pF
ZI
D98AU905
3) TTL Schmitt Trigger Inpud Pad Buffer, 3V capable / Pin numbers:17, 60, 63
INPUT PIN A
D98AU906
A
Z
CAPACITANCE TBD
4) TTL Inpud Pad Buffer, 3V capable with Pull-Up / Pin numbers:15, 16
INPUT PIN A
D98AU907
A
Z
CAPACITANCE TBD
5) TTL Schmitt Trigger Bidir Pad Buffer, with Pull-up, 4mA, with slew rate control / 3V capable
Pin numbers: 26, 27, 28, 31, 32, 33, 34, 35, 44, 45, 46, 47, 48, 49, 50, 51, 64
EN IO A
INPUT PIN IO
CAPACITANCE TBD
OUTPUT PIN IO
MAX LOAD 100pF
ZI
D00AU1150
6) TTL Input Pad Buffer, 3V capable, with pull down / Pin numbers: 12, 13, 14, 55
A Z
INPUT PIN A
CAPACITANCE TBD
D00AU1222
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STA016T
4 COMMAND PROTOCOL CONFIGURATION
General Information About The Command Protocol I2C protocol :
CD_module & mmdsp are using an I2C protocol to communicate : CD_module is master of the I2C protocol, and can access (in read and write mode) host registers of the sta016 to write commands to the mmdsp and to read request from the mmdsp. It must use following I2C syntax : device_address, host_register_number, host_register_value where : for a write acces, device_address is 0x86. for a read acces, device_address is 0x87.
Writing a command to mmdsp :
CD_module write its command inside dedicated host registers (mainly H64 to H69), then it must signals the writing of this command to mmdsp by sending the interrupt IT_CMD to the core of mmdsp. Note that IT_CMD is generated by cd_module threw a falling edge on the input line number 0 of the sta016 (the INTLINE[0] pin).
Reading a request from mmdsp :
MMDSP write its request inside dedicated host registers (mainly H70 to H78 and H134 to H169), then it signals to cd_module that it must read a request by sending the interrupt IT_REQ. Note that IT_REQ interrupt is generated by mmdsp on the IRQB pin of sta016. Note also that once it has finished to read the message, cd_module must always acknowledge it by reading H10.
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STA016T
Figure 4. Block diagram for running the CD application.
Hxx: host register number xx
power on
cd inserted ?
no
write 1 in SOFT_RESET write 0 in CK_CMD wait IT_REQ with 35 in H70 start cd-rom application: write 0 in H85, then 1 in H86 wait IT_REQ with 112 in H70 send play_music command : write 112 in H64 send IT_CMD cd ejected?
yes
yes send pause command : write 2 in H64 send IT_CMD run the other application return to cd?
run other application? any command?
no
send other command : write in H64 send IT_CMD no
yes
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STA016T
Figure 5. Block diagram for answer to a sector request from dsp.
Hxx: host register number xx
power on
IT_REQ occured
H70==18 read minute in H71 read second in H72 read frame in H73 acknowledge IT_REQ acknowledge IT_REQ move the pick-up according to m,s,f
please check with rest of documentation
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STA016T
DIM. MIN. A A1 A2 B C D D1 D3 e E E1 E3 L L1 K 0.40 0.05 1.35 0.18 0.12
mm TYP. MAX. 1.60 0.15 1.40 0.23 0.16 12.00 10.00 7.50 0.50 12.00 10.00 7.50 0.60 1.00 0.75 1.45 0.28 0.20 0.002 0.053 0.007 MIN.
inch TYP. MAX. 0.063 0.006 0.055 0.009 0.057 0.011
OUTLINE AND MECHANICAL DATA
0.0047 0.0063 0.0079 0.472 0.394 0.295 0.0197 0.472 0.394 0.295 0.0157 0.0236 0.0295 0.0393
0(min.), 7(max.)
TQFP64
D D1 A D3 A1 48 49 33 32
0.10mm Seating Plane
A2
B
E3
E1
64 1 e 16
17 C
L1
E
L
K
TQFP64
44/45
B
STA016T
Note:1 STA016 is a device based on an integrated DSP core. Some of the I2C registers default values are loaded after an internal DSP boot operation. The bootstrap time is 60 micro second. Only after this time lenght, the data in the register can be considered stable.
Information furnished is believed to be accurate and reliable. However, STMicroelectronics assumes no responsibility for the consequences of use of such information nor for any infringement of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of STMicroelectronics. Specifications mentioned in this publication are subject to change without notice. This publication supersedes and replaces all information previously supplied. STMicroelectronics products are not authorized for use as critical components in lif e support devices or systems without express written approval of STMicroelectronics. The ST logo is a registered trademark of STMicroelectronics 2002 STMicroelectronics - All Rights Reserved STMicroelectronics GROUP OF COMPANIES Australia - Brazil - Canada - China - Finland - France - Germany - Hong Kong - India - Israel - Italy - Japan -Malaysia - Malta - Morocco Singapore - Spain - Sweden - Switzerland - United Kingdom - United States. http:/ /www.st.com
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